Tutorial
Multiple Output LDO Regulator and Controller ICs
Multiple output controller ICs consist of two or more combinations of LDO regulator or converters. They can be controllers that employs external power switches or regulators with an internal power switch. One possibility is a 5V output and a 3.3V output for processor and logic applications.
These devices are used in ac powerline and battery-powered applications. Some of the more sophisticated ICs include supervisory and power sequencing capability.
Among the features found in multiple output controller ICs are:
- Fixed or adjustable outputs
- Soft-start
- Fixed or variable switching frequency
- Undervoltage lockout (UVLO)
- Thermal protection
- Power Good output
- Current limit
- Overvoltage protection
- Enable/disable
- Independently regulated outputs
- Power sequencing control
Following are typical examples of these ICs.
1. This family ICs provide a complete power management solution for DSP, processor power, ASIC, FPGA, and digital applications that require dual output voltage regulators. Differentiated features, such as accuracy, fast transient response, power on reset, manual reset inputs, and enable function, provide a complete system solution.
These voltage regulators offer dual outputs with power up sequence control, which is designed primarily for DSP applications. They have extremely low noise output performance without using any added filter bypass capacitors and are designed to have a fast transient response and be stable with 10µF low ESR capacitors.
Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (typically 83 mV on Regulator 1) and is directly proportional to the output current. Additionally, since the PMOS pass element is a voltage-driven device, the quiescent current is very low and independent of output loading (maximum of 230 µA over the full range of output current). This LDO family also features a sleep mode; applying a high signal to EN (enable) shuts down both regulators, reducing the input current to 1 µA at TJ = 25°C. The device is enabled when the EN pin is connected to a low-level input voltage. The output voltages of the two regulators are sensed at the VSENSE1 and VSENSE2 pins, respectively.
The input signal at the SEQ pin controls the power-up sequence of the two regulators. When the device is enabled and the SEQ terminal is pulled high or left open, VOUT2 turns on first and VOUT1 remains off until VOUT2 reaches approximately 83% of its regulated output voltage. At that time VOUT1 is turned on. If VOUT2 is pulled below 83% (i.e. overload condition) VOUT1 is turned off. Pulling the SEQ terminal low, reverses the power-up order and VOUT1 is turned on first. The SEQ pin is connected to an internal pull-up current source.
2. A dual-output, low-dropout voltage regulator IC has integrated RESET, power on reset (POR) and power good (PG) functions. Quiescent current is typically 190µA at full load. Differentiated features, such as accuracy, fast transient response, supervisory circuit (power on reset), manual reset input, and independent enable functions provide a complete system solution. This family of voltage regulators have extremely low noise output performance without using any added filter bypass capacitors and are designed to have a fast transient response and be stable with 10µF low ESR capacitors.
Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (typically 170 mV on Regulator 1) and is directly proportional to the output current. Additionally, since the PMOS pass element is a voltage-driven device, the quiescent current is very low and independent<