DDR Memory Termination Supply ICs

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Low end of the dc input voltage (Short Name:VinL)
High end of the dc input voltage (Short Name:VinH)
Output current in amperes. (Short Name:Iout)
Low end of switching frequency in MHz. (Short Name:FreqL)
High end of switching frequency in MHz. (Short Name:FreqH)
Double Data Rate Memory Version 1 (Short Name:DDR1)
Double Data Rate Memory Version 2 (Short Name:DDR2)

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DDR Memory Termination Supply ICs

DDRAM (Double Data RAM) evolved from SDRAM to keep pace with faster microprocessors. DDR accesses data on the positive and negative going transitions of computer clock cycle, whereas SDRAM accesses data on just a single signal transition of the clock. Currently, the DDRAM standards are PC1600, PC2100, and PC2700, which refer to the total memory bandwidth.

Older SDRAM standards listed the speed rating in MHz, such as PC66, PC100, and PC133. In another difference, SDRAM memory cards have 168 pins, compared with 184 pins for the DDRAM cards; therefore, the two types of memory are not interchangeable. For most applications, DDR memories should outperform the SDRAM PC100/ PC133 by about 10%.

DDR memories require terminal regulators, power supplies that minimize timing skew and power dissipation. The voltages involved in this termination process are VDDQ, VTT, and VREF. According to the JEDEC specification: VTT = 0.5 (VDDQ), VREF is a buffered reference voltage that also tracks 0.5(VDDQ) and VTT must track VREF with <40mV offset regardless of variations in voltage, temperature, and noise.

DDR memory systems employ Series Stub Termination Logic (SSTL) that improves signal integrity of the data transmission across the memory bus. This termination scheme is essential to prevent data error from signal reflections while transmitting at high frequencies encountered with DDR RAM. This termination configuration prevents data error from signal reflections while transmitting at the high frequencies associated with DDR memory. It involves the use of the termination regulator and termination resistors that regulate the voltage to 0.5(VDDQ).

Future DDR memories may require a new generation of termination regulators because JEDEC (the industry standards body) has approved the preliminary spec for the next generation DDR-II main memory chip, which is expected to be in production in 2003. DDR-II is expected to be lower voltage at 1.8V, with speeds up to 533MHz.

In the preliminary spec, JEDEC approved 400 and 533MHz DDR main memory chips. Comparable DDR memory modules would carry the PC3200 nomenclature for a 3.2Gbyte/s bandwidth using the 400MHz chip, and PC4300, with a bandwidth of 4.3GBytes/s for the 533MHz chip. The JEDEC memory group is now looking at a DDR III specification for a system solution to follow in the 2004 to 2005 time period. DDR III specifications will cover details of the modules, components, registers, and buffers.

Besides DDR memory for CPU main memories the industry is also looking at a new generation of DDR memories for graphic cards. These graphic DDR memories will probably be different from those for main memories. Termination memory supplies for the graphic memories could be different from those intended for main memories.